Benchmark CPA/CoVeriTest TBF Test-Suite Validator
Tool CPAchecker 1.8-svn 30375 Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon049; apollon085; apollon116]
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-05 21:05:56 CET 2019-02-06 05:30:26 CET
Run set coveritest.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-coveritest.test-comp19_prop-coverage-branches.ReachSafety-BitVectors
Options -benchmark -heap 10000M -testcomp19 --verbose --sequence-file cov-seq.txt -r --test-suite ../../results-verified/coveritest.2019-02-05_2105.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml done .983 prog tests 54 inspect 34 15   810 330 1.2   0      true prog tests 1 inspect
98.3  100    .32 .33 17 1.2  0  
bitvector/byte_add_1-1.yml timeout .733 prog tests 39 inspect 900 860   4200 12000 1.5   0      unknown prog tests 0 inspect
73.3  82.8  .26 .24 16 .86 0  
bitvector/byte_add_2-2.yml timeout .75  prog tests 40 inspect 900 860   3700 11000 1.5   0      unknown prog tests 0 inspect
75.0  82.8  .26 .24 18 .88 0  
bitvector/gcd_1.yml done .833 prog tests 9 inspect 29 23   1400 300 .029 0      unknown prog tests 0 inspect
83.3  94.7  .15 .14 17 .21 0  
bitvector/gcd_2.yml done .9   prog tests 9 inspect 26 20   1600 340 .049 0      unknown prog tests 0 inspect
90.0  94.7  .15 .15 16 .21 0  
bitvector/gcd_3.yml done .9   prog tests 9 inspect 130 120   1500 1600 .074 0      unknown prog tests 0 inspect
90.0  94.7  .16 .15 16 .21 0  
bitvector/interleave_bits.yml done .75  prog tests 3 inspect 26 18   2300 290 .049 0      unknown prog tests 0 inspect
75.0  95.8  .14 .14 17 .11 0  
bitvector/modulus-2.yml timeout .9   prog tests 9 inspect 900 890   590 13000 .57  0      unknown prog tests 0 inspect
90.0  95.2  .15 .19 17 .21 0  
bitvector/num_conversion_2.yml done .833 prog tests 5 inspect 36 15   1100 310 1.3   0      unknown prog tests 0 inspect
83.3  93.8  .13 .13 16 .14 0  
bitvector/parity.yml done .875 prog tests 6 inspect 180 140   2500 1900 4.5   0      unknown prog tests 0 inspect
87.5  95.7  .13 .13 16 .16 0  
bitvector/s3_clnt_1.BV.c.cil-1.yml done .790 prog tests 111 inspect 220 180   2300 2400 2.9   0      unknown prog tests 0 inspect
79.0  88.5  .68 .64 17 7.3  0  
bitvector/s3_clnt_1.BV.c.cil-2.yml done .926 prog tests 135 inspect 58 33   1200 600 1.3   0      true prog tests 1 inspect
92.6  94.1  .98 .94 17 8.9  0  
bitvector/s3_clnt_2.BV.c.cil-1.yml done .775 prog tests 107 inspect 120 87   2000 1500 2.7   0      unknown prog tests 0 inspect
77.5  88.1  .75 .73 17 7.1  0  
bitvector/s3_clnt_2.BV.c.cil-2.yml done .938 prog tests 132 inspect 55 30   1200 610 1.3   0      true prog tests 1 inspect
93.8  95.8  .92 .93 17 8.7  0  
bitvector/s3_clnt_3.BV.c.cil-1.yml done .778 prog tests 109 inspect 270 210   3600 3200 10     0      unknown prog tests 0 inspect
77.8  88.2  .73 .70 17 7.2  0  
bitvector/s3_clnt_3.BV.c.cil-2.yml done .636 prog tests 88 inspect 140 100   2200 1900 4.8   0      true prog tests 1 inspect
63.6  71.8  .69 .68 17 5.8  0  
bitvector/s3_srvr_1.BV.c.cil.yml done .782 prog tests 104 inspect 180 130   2400 2100 3.9   0      unknown prog tests 0 inspect
78.2  80.8  .72 .77 17 8.1  0  
bitvector/s3_srvr_1_alt.BV.c.cil.yml timeout .0   prog tests 143 inspect 900 860   2100 9700 3.8   0      unknown prog tests 0 inspect
.00 7.03 .90 .86 17 11    0  
bitvector/s3_srvr_3.BV.c.cil.yml done .822 prog tests 103 inspect 120 87   1600 1300 1.5   0      unknown prog tests 0 inspect
82.2  84.5  .71 .68 17 7.6  0  
bitvector/s3_srvr_3_alt.BV.c.cil.yml done .822 prog tests 103 inspect 110 87   1700 1300 1.4   0      unknown prog tests 0 inspect
82.2  84.6  .72 .69 17 7.6  0  
bitvector/soft_float_1-2.c.cil.yml done .689 prog tests 41 inspect 30 9.4 890 250 1.7   0      unknown prog tests 0 inspect
68.9  69.8  .28 .27 17 1.2  0  
bitvector/soft_float_1-3.c.cil.yml done .703 prog tests 41 inspect 29 8.8 750 230 1.5   0      true prog tests 1 inspect
70.3  70.4  .27 .25 16 1.2  0  
bitvector/soft_float_2.c.cil.yml done .688 prog tests 29 inspect 160 120   2800 1800 3.6   0      unknown prog tests 0 inspect
68.8  70.2  .24 .23 17 .78 0  
bitvector/soft_float_3.c.cil.yml done .708 prog tests 30 inspect 200 150   2800 2100 3.7   0      unknown prog tests 0 inspect
70.8  71.0  .25 .23 16 .81 0  
bitvector/soft_float_4-2.c.cil.yml done .595 prog tests 24 inspect 310 260   3000 3800 11     0      unknown prog tests 0 inspect
59.5  64.6  .20 .19 16 .66 0  
bitvector/soft_float_4-3.c.cil.yml done .619 prog tests 24 inspect 340 270   4200 3900 19     0      true prog tests 1 inspect
61.9  65.3  .23 .21 16 .66 0  
bitvector/soft_float_5.c.cil.yml done .688 prog tests 29 inspect 160 120   3700 1800 3.3   0      unknown prog tests 0 inspect
68.8  70.2  .24 .27 17 .78 0  
bitvector/sum02-1.yml timeout .5   prog tests 4 inspect 900 770   6500 9600 41     .0041 unknown prog tests 0 inspect
50.0  88.9  .12 .15 16 .13 0  
bitvector/sum02-2.yml timeout .5   prog tests 5 inspect 900 770   7400 12000 37     0      unknown prog tests 0 inspect
50.0  92.3  .12 .12 16 .14 0  
bitvector-regression/recHanoi03-1.yml out of memory .75  prog tests 5 inspect 140 77   15000 1400 60     0      unknown prog tests 0 inspect
75.0  91.7  .13 .13 16 .14 0  
bitvector-loops/diamond_2-1.yml done 1.0   prog tests 23 inspect 26 7.1 970 210 2.1   0      true prog tests 1 inspect
100    100    .19 .18 16 .44 0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml timeout .875 prog tests 6 inspect 900 880   1600 14000 1.3   0      unknown prog tests 0 inspect
87.5  94.7  .14 .14 16 .16 0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 32 24.0 9400 8200 89000 120000 230 .0041 32 2400 2660 12 12 540 91 0  
Run set coveritest.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-coveritest.test-comp19_prop-coverage-branches.ReachSafety-BitVectors