Benchmark CPA/Tiger-MGP TBF Test-Suite Validator
Tool CPAchecker 1.8-svn 30541M Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-05 21:13:54 CET 2019-02-06 06:15:02 CET
Run set cpa-tiger.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-cpa-tiger.test-comp19_prop-coverage-branches.ReachSafety-BitVectors
Options -benchmark -heap 10000M -tigertestcomp19 --verbose --sequence-file cov-seq.txt -r --test-suite ../../results-verified/cpa-tiger.2019-02-05_2113.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml timeout .967 prog tests 13 inspect 900   870   10000 11000 .0041 0   true prog tests 1 inspect
96.7  100    .17 .16 17 .33  0  
bitvector/byte_add_1-1.yml timeout .733 prog tests 12 inspect 900   870   8300 9800 .0041 0   unknown prog tests 0 inspect
73.3  82.8  .16 .15 17 .31  0  
bitvector/byte_add_2-2.yml timeout .717 prog tests 10 inspect 900   870   8700 11000 .0041 0   unknown prog tests 0 inspect
71.7  82.8  .15 .15 16 .27  0  
bitvector/gcd_1.yml true .833 prog tests 6 inspect 9.0 7.1 290 94 .0041 0   unknown prog tests 0 inspect
83.3  94.7  .13 .13 16 .16  0  
bitvector/gcd_2.yml unknown .9   prog tests 5 inspect 8.8 6.7 290 110 .0041 0   unknown prog tests 0 inspect
90.0  94.7  .13 .13 17 .14  0  
bitvector/gcd_3.yml unknown .9   prog tests 6 inspect 93   91   300 1100 .0041 0   unknown prog tests 0 inspect
90.0  94.7  .14 .14 16 .16  0  
bitvector/interleave_bits.yml true .75  prog tests 3 inspect 10   4.5 460 92 .0041 0   unknown prog tests 0 inspect
75.0  95.8  .15 .18 16 .11  0  
bitvector/modulus-2.yml timeout .9   prog tests 4 inspect 900   900   420 13000 .0041 0   unknown prog tests 0 inspect
90.0  95.2  .13 .13 17 .13  0  
bitvector/num_conversion_2.yml true .833 prog tests 4 inspect 14   11   440 140 .0041 0   unknown prog tests 0 inspect
83.3  93.8  .13 .13 16 .13  0  
bitvector/parity.yml unknown .875 prog tests 6 inspect 120   120   660 1600 .0041 0   unknown prog tests 0 inspect
87.5  95.7  .13 .15 16 .13  0  
bitvector/s3_clnt_1.BV.c.cil-1.yml timeout .599 prog tests 25 inspect 900   890   660 14000 .0041 0   unknown prog tests 0 inspect
59.9  71.8  .31 .30 17 1.7   0  
bitvector/s3_clnt_1.BV.c.cil-2.yml true .938 prog tests 83 inspect 59   48   710 700 .0041 0   true prog tests 1 inspect
93.8  95.6  .65 .72 17 5.5   0  
bitvector/s3_clnt_2.BV.c.cil-1.yml timeout .619 prog tests 30 inspect 900   890   500 11000 .0041 0   unknown prog tests 0 inspect
61.9  75.8  .33 .40 17 2.0   0  
bitvector/s3_clnt_2.BV.c.cil-2.yml true .938 prog tests 87 inspect 33   22   690 340 .0041 0   true prog tests 1 inspect
93.8  95.8  .69 .70 17 5.8   0  
bitvector/s3_clnt_3.BV.c.cil-1.yml timeout .611 prog tests 29 inspect 900   890   860 13000 .0041 0   unknown prog tests 0 inspect
61.1  76.0  .33 .31 17 2.0   0  
bitvector/s3_clnt_3.BV.c.cil-2.yml timeout .549 prog tests 26 inspect 930   920   510 12000 .0041 0   true prog tests 1 inspect
54.9  66.5  .38 .37 17 1.8   0  
bitvector/s3_srvr_1.BV.c.cil.yml unknown .782 prog tests 55 inspect 330   320   640 4200 .0041 0   unknown prog tests 0 inspect
78.2  80.8  .47 .52 17 4.3   0  
bitvector/s3_srvr_1_alt.BV.c.cil.yml timeout .0   prog tests 39 inspect 900   890   600 9500 .0041 0   unknown prog tests 0 inspect
.00 7.03 .39 .37 17 3.1   0  
bitvector/s3_srvr_3.BV.c.cil.yml unknown .822 prog tests 48 inspect 520   500   650 7200 .0041 0   unknown prog tests 0 inspect
82.2  84.5  .54 .51 17 3.6   0  
bitvector/s3_srvr_3_alt.BV.c.cil.yml timeout .644 prog tests 28 inspect 900   890   840 9600 .0041 0   unknown prog tests 0 inspect
64.4  72.5  .36 .34 17 2.1   0  
bitvector/soft_float_1-2.c.cil.yml true .689 prog tests 24 inspect 19   12   440 220 .0041 0   unknown prog tests 0 inspect
68.9  69.8  .21 .20 17 .76  0  
bitvector/soft_float_1-3.c.cil.yml true .703 prog tests 26 inspect 16   8.9 450 170 .0041 0   true prog tests 1 inspect
70.3  70.4  .23 .22 17 .82  0  
bitvector/soft_float_2.c.cil.yml true .688 prog tests 15 inspect 160   140   890 1900 .0041 0   unknown prog tests 0 inspect
68.8  70.2  .21 .22 16 .44  0  
bitvector/soft_float_3.c.cil.yml timeout .542 prog tests 6 inspect 900   890   1100 6800 .0041 0   unknown prog tests 0 inspect
54.2  59.5  .14 .14 16 .22  0  
bitvector/soft_float_4-2.c.cil.yml unknown .571 prog tests 11 inspect 690   680   800 8000 .0041 0   unknown prog tests 0 inspect
57.1  63.0  .16 .15 16 .34  0  
bitvector/soft_float_4-3.c.cil.yml unknown .595 prog tests 14 inspect 580   570   490 7900 .0041 0   true prog tests 1 inspect
59.5  63.8  .18 .17 17 .41  0  
bitvector/soft_float_5.c.cil.yml true .688 prog tests 16 inspect 160   140   880 1800 .0041 0   unknown prog tests 0 inspect
68.8  70.2  .18 .18 16 .46  0  
bitvector/sum02-1.yml unknown .5   prog tests 2 inspect 470   450   1500 5400 .0041 0   unknown prog tests 0 inspect
50.0  88.9  .13 .13 16 .094 0  
bitvector/sum02-2.yml timeout .5   prog tests 1 inspect 900   870   3800 9900 .0041 0   unknown prog tests 0 inspect
50.0  92.3  .12 .12 16 .078 0  
bitvector-regression/recHanoi03-1.yml error (recursion) .125 prog tests 1 inspect 2.9 1.3 260 24 .0041 0   unknown prog tests 0 inspect
12.5  33.3  .12 .12 17 .078 0  
bitvector-loops/diamond_2-1.yml unknown 1.0   prog tests 7 inspect 4.9 2.2 300 42 .0041 0   true prog tests 1 inspect
100    100    .14 .16 16 .18  0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml timeout .75  prog tests 2 inspect 930   930   540 14000 .0041 0   unknown prog tests 0 inspect
75.0  94.7  .12 .12 16 .094 0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 32 22.3  15000 15000 48000 180000 .13  0   32 2230 2530 7.8 7.9 530 38 0  
Run set cpa-tiger.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-cpa-tiger.test-comp19_prop-coverage-branches.ReachSafety-BitVectors