Benchmark ESBMC-falsif TBF Test-Suite Validator
Tool ESBMC version 6.0.0 64-bit x86_64 linux Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-05 21:11:17 CET 2019-02-06 06:16:01 CET
Run set esbmc-falsi.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-esbmc-falsi.test-comp19_prop-coverage-branches.ReachSafety-BitVectors
Options -s falsi --verbose --sequence-file cov-seq.txt -r --test-suite ../../results-verified/esbmc-falsi.2019-02-05_2111.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml unknown .0  prog tests 0 inspect .022 .022 5.7 .12  0   0   error (0) prog tests 0 inspect
0 0 .061 .062 9.0 0   0  
bitvector/byte_add_1-1.yml unknown .0  prog tests 0 inspect .042 .043 5.7 .11  0   0   error (0) prog tests 0 inspect
0 0 .059 .060 9.0 0   0  
bitvector/byte_add_2-2.yml unknown .0  prog tests 0 inspect .025 .026 5.7 .094 0   0   error (0) prog tests 0 inspect
0 0 .059 .060 9.0 0   0  
bitvector/gcd_1.yml unknown .0  prog tests 0 inspect .028 .030 5.6 .16  0   0   error (0) prog tests 0 inspect
0 0 .062 .063 9.0 0   0  
bitvector/gcd_2.yml unknown .0  prog tests 0 inspect .025 .026 5.7 .14  0   0   error (0) prog tests 0 inspect
0 0 .060 .061 8.9 0   0  
bitvector/gcd_3.yml unknown .0  prog tests 0 inspect .025 .026 5.7 .12  0   0   error (0) prog tests 0 inspect
0 0 .061 .062 8.9 0   0  
bitvector/interleave_bits.yml unknown .0  prog tests 0 inspect .037 .038 5.6 .061 0   0   error (0) prog tests 0 inspect
0 0 .061 .062 9.0 0   0  
bitvector/modulus-2.yml unknown .0  prog tests 0 inspect .024 .025 5.7 .096 0   0   error (0) prog tests 0 inspect
0 0 .059 .059 8.9 0   0  
bitvector/num_conversion_2.yml unknown .0  prog tests 0 inspect .027 .029 5.7 .21  0   0   error (0) prog tests 0 inspect
0 0 .061 .061 8.9 0   0  
bitvector/parity.yml unknown .0  prog tests 0 inspect .022 .023 5.7 .14  0   0   error (0) prog tests 0 inspect
0 0 .060 .060 8.9 0   0  
bitvector/s3_clnt_1.BV.c.cil-1.yml unknown .0  prog tests 0 inspect .017 .022 5.7 .17  0   0   error (0) prog tests 0 inspect
0 0 .068 .068 9.0 0   0  
bitvector/s3_clnt_1.BV.c.cil-2.yml unknown .0  prog tests 0 inspect .026 .028 5.7 .17  0   0   error (0) prog tests 0 inspect
0 0 .062 .063 8.9 0   0  
bitvector/s3_clnt_2.BV.c.cil-1.yml unknown .0  prog tests 0 inspect .023 .023 5.7 .11  0   0   error (0) prog tests 0 inspect
0 0 .057 .058 9.0 0   0  
bitvector/s3_clnt_2.BV.c.cil-2.yml unknown .0  prog tests 0 inspect .022 .023 5.8 .11  0   0   error (0) prog tests 0 inspect
0 0 .060 .061 9.0 0   0  
bitvector/s3_clnt_3.BV.c.cil-1.yml unknown .0  prog tests 0 inspect .023 .023 5.6 .12  0   0   error (0) prog tests 0 inspect
0 0 .059 .060 9.0 0   0  
bitvector/s3_clnt_3.BV.c.cil-2.yml unknown .0  prog tests 0 inspect .026 .028 5.6 .22  0   0   error (0) prog tests 0 inspect
0 0 .064 .065 9.0 0   0  
bitvector/s3_srvr_1.BV.c.cil.yml unknown .0  prog tests 0 inspect .027 .029 5.6 .19  0   0   error (0) prog tests 0 inspect
0 0 .060 .061 9.0 0   0  
bitvector/s3_srvr_1_alt.BV.c.cil.yml unknown .0  prog tests 0 inspect .048 .049 5.8 .059 0   0   error (0) prog tests 0 inspect
0 0 .060 .060 9.0 0   0  
bitvector/s3_srvr_3.BV.c.cil.yml unknown .0  prog tests 0 inspect .024 .025 5.6 .12  0   0   error (0) prog tests 0 inspect
0 0 .057 .058 8.9 0   0  
bitvector/s3_srvr_3_alt.BV.c.cil.yml unknown .0  prog tests 0 inspect .035 .036 5.7 .10  0   0   error (0) prog tests 0 inspect
0 0 .062 .062 8.9 0   0  
bitvector/soft_float_1-2.c.cil.yml unknown .0  prog tests 0 inspect .053 .054 5.6 .11  0   0   error (0) prog tests 0 inspect
0 0 .058 .058 8.9 0   0  
bitvector/soft_float_1-3.c.cil.yml unknown .0  prog tests 0 inspect .026 .028 5.7 .21  0   0   error (0) prog tests 0 inspect
0 0 .057 .058 9.0 0   0  
bitvector/soft_float_2.c.cil.yml unknown .0  prog tests 0 inspect .033 .036 5.7 .19  0   0   error (0) prog tests 0 inspect
0 0 .060 .062 8.9 0   0  
bitvector/soft_float_3.c.cil.yml unknown .0  prog tests 0 inspect .023 .023 5.6 .13  0   0   error (0) prog tests 0 inspect
0 0 .059 .060 8.9 0   0  
bitvector/soft_float_4-2.c.cil.yml unknown .0  prog tests 0 inspect .023 .026 5.8 .15  0   0   error (0) prog tests 0 inspect
0 0 .056 .057 8.9 0   0  
bitvector/soft_float_4-3.c.cil.yml unknown .0  prog tests 0 inspect .025 .026 5.8 .13  0   0   error (0) prog tests 0 inspect
0 0 .060 .061 9.0 0   0  
bitvector/soft_float_5.c.cil.yml unknown .0  prog tests 0 inspect .025 .026 5.7 .053 0   0   error (0) prog tests 0 inspect
0 0 .060 .062 9.0 0   0  
bitvector/sum02-1.yml unknown .0  prog tests 0 inspect .030 .033 5.7 .15  0   0   error (0) prog tests 0 inspect
0 0 .060 .061 9.0 0   0  
bitvector/sum02-2.yml unknown .0  prog tests 0 inspect .027 .029 5.7 .089 0   0   error (0) prog tests 0 inspect
0 0 .074 .074 8.9 0   0  
bitvector-regression/recHanoi03-1.yml unknown .0  prog tests 0 inspect .029 .031 5.7 .19  0   0   error (0) prog tests 0 inspect
0 0 .065 .072 8.9 0   0  
bitvector-loops/diamond_2-1.yml unknown .0  prog tests 0 inspect .022 .024 5.7 .097 0   0   error (0) prog tests 0 inspect
0 0 .067 .067 8.9 0   0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml unknown .0  prog tests 0 inspect .028 .032 5.7 .076 0   0   error (0) prog tests 0 inspect
0 0 .090 .093 8.9 0   0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 32 .0  .89 .94 180 4.2 0   0   32 0 0 2.0 2.0 290 0   0  
Run set esbmc-falsi.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-esbmc-falsi.test-comp19_prop-coverage-branches.ReachSafety-BitVectors