Benchmark FairFuzz TBF Test-Suite Validator
Tool FairFuzz TC-0.0.2 Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-08 09:39:09 CET 2019-02-08 13:22:04 CET
Run set fairfuzz.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-fairfuzz.test-comp19_prop-coverage-branches.ReachSafety-BitVectors
Options --verbose --sequence-file cov-seq.txt -r --test-suite ../../results-verified/fairfuzz.2019-02-08_0939.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml false(unreach-call) .983  prog tests 28 inspect 42   39   17 110 .30 0   true prog tests 1 inspect
98.3  100   .22  .20  17   .64  0  
bitvector/byte_add_1-1.yml done .717  prog tests 9 inspect 21   19   17 95 .30 0   unknown prog tests 0 inspect
71.7  82.8 .15  .14  16   .25  0  
bitvector/byte_add_2-2.yml done .75   prog tests 9 inspect 51   47   19 120 .30 0   unknown prog tests 0 inspect
75.0  82.8 .15  .18  17   .25  0  
bitvector/gcd_1.yml done .75   prog tests 4 inspect 18   17   16 48 .29 0   unknown prog tests 0 inspect
75.0  94.7 .12  .12  16   .13  0  
bitvector/gcd_2.yml done .9    prog tests 6 inspect 27   25   18 100 .28 0   unknown prog tests 0 inspect
90.0  94.7 .13  .13  16   .16  0  
bitvector/gcd_3.yml done .9    prog tests 8 inspect 26   24   17 110 .28 0   unknown prog tests 0 inspect
90.0  94.7 .14  .14  17   .19  0  
bitvector/interleave_bits.yml done .75   prog tests 1 inspect 20   18   15 98 .34 0   unknown prog tests 0 inspect
75.0  95.8 .14  .14  16   .078 0  
bitvector/modulus-2.yml timeout .9    prog tests 7 inspect 900   900   11 13000 .50 0   unknown prog tests 0 inspect
90.0  95.2 .14  .15  17   .18  0  
bitvector/num_conversion_2.yml done .667  prog tests 1 inspect 20   18   16 91 .21 0   unknown prog tests 0 inspect
66.7  87.5 .11  .11  16   .078 0  
bitvector/parity.yml done .875  prog tests 6 inspect 9.1 8.4 10 19 .27 0   unknown prog tests 0 inspect
87.5  95.7 .13  .13  17   .16  0  
bitvector/s3_clnt_1.BV.c.cil-1.yml done .753  prog tests 34 inspect 270   250   17 890 .34 0   unknown prog tests 0 inspect
75.3  87.1 .35  .34  17   2.3   0  
bitvector/s3_clnt_1.BV.c.cil-2.yml false(unreach-call) .790  prog tests 48 inspect 550   510   19 2500 .55 0   true prog tests 1 inspect
79.0  90.0 .49  .46  17   3.2   0  
bitvector/s3_clnt_2.BV.c.cil-1.yml done .025  prog tests 1 inspect 37   34   13 100 .25 0   unknown prog tests 0 inspect
2.50 19.1 .20  .20  17   .12  0  
bitvector/s3_clnt_2.BV.c.cil-2.yml done .025  prog tests 1 inspect 26   24   14 120 .25 0   unknown prog tests 0 inspect
2.50 19.2 .20  .20  17   .12  0  
bitvector/s3_clnt_3.BV.c.cil-1.yml done .0309 prog tests 1 inspect 40   37   14 130 .25 0   unknown prog tests 0 inspect
3.09 19.5 .20  .20  17   .12  0  
bitvector/s3_clnt_3.BV.c.cil-2.yml done .0309 prog tests 1 inspect 37   35   14 98 .25 0   unknown prog tests 0 inspect
3.09 19.3 .20  .20  17   .12  0  
bitvector/s3_srvr_1.BV.c.cil.yml timeout .771  prog tests 109 inspect 900   850   21 3000 1.0  0   unknown prog tests 0 inspect
77.1  80.5 .79  .88  18   8.5   0  
bitvector/s3_srvr_1_alt.BV.c.cil.yml couldn't run: all seeds time out or crash .0    prog tests 0 inspect 3.2 3.2 11 43 .26 0   unknown prog tests 0 inspect
0    0   .060 .061 8.9 0     0  
bitvector/s3_srvr_3.BV.c.cil.yml done .805  prog tests 94 inspect 590   560   19 1800 .76 0   unknown prog tests 0 inspect
80.5  84.0 .67  .68  17   7.0   0  
bitvector/s3_srvr_3_alt.BV.c.cil.yml done .810  prog tests 103 inspect 860   800   20 2800 1.0  0   unknown prog tests 0 inspect
81.0  84.3 .74  .83  17   7.6   0  
bitvector/soft_float_1-2.c.cil.yml timeout .662  prog tests 113 inspect 900   900   14 13000 .99 0   unknown prog tests 0 inspect
66.2  67.5 .56  .57  18   3.3   0  
bitvector/soft_float_1-3.c.cil.yml false(unreach-call) .689  prog tests 137 inspect 170   150   22 500 .44 0   true prog tests 1 inspect
68.9  69.2 .63  .71  17   4.0   0  
bitvector/soft_float_2.c.cil.yml done .625  prog tests 103 inspect 61   54   20 480 .36 0   unknown prog tests 0 inspect
62.5  65.7 .51  .56  17   2.6   0  
bitvector/soft_float_3.c.cil.yml done .667  prog tests 98 inspect 230   210   21 900 .43 0   unknown prog tests 0 inspect
66.7  67.9 .55  .50  17   2.5   0  
bitvector/soft_float_4-2.c.cil.yml timeout .571  prog tests 120 inspect 900   900   15 13000 1.1  0   unknown prog tests 0 inspect
57.1  63.0 .57  .58  17   3.0   0  
bitvector/soft_float_4-3.c.cil.yml false(unreach-call) .595  prog tests 126 inspect 120   110   23 520 .36 0   true prog tests 1 inspect
59.5  63.8 .60  .60  17   3.2   0  
bitvector/soft_float_5.c.cil.yml done .625  prog tests 93 inspect 250   230   22 770 .36 0   unknown prog tests 0 inspect
62.5  65.7 .47  .46  18   2.4   0  
bitvector/sum02-1.yml false(unreach-call) .875  prog tests 34 inspect 700   700   10 9100 .34 0   true prog tests 1 inspect
87.5  100   66     66     16   .62  0  
bitvector/sum02-2.yml done .5    prog tests 22 inspect 880   880   10 10000 .50 0   unknown prog tests 0 inspect
50.0  92.3 40     40     17   .42  0  
bitvector-regression/recHanoi03-1.yml false(unreach-call) .875  prog tests 29 inspect 680   680   10 8600 .34 0   true prog tests 1 inspect
87.5  100   .27  .35  23   .54  0  
bitvector-loops/diamond_2-1.yml false(unreach-call) 1.0    prog tests 2 inspect 19   17   16 85 .20 0   true prog tests 1 inspect
100    100   .12  .12  17   .094 0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml false(unreach-call) 1.0    prog tests 12 inspect 58   53   16 210 .29 0   true prog tests 1 inspect
100    100   .17  .20  16   .26  0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 32 20.9  9400 9100 520 83000 14   0   32 2090 2380 120 120 540 54 0  
Run set fairfuzz.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-fairfuzz.test-comp19_prop-coverage-branches.ReachSafety-BitVectors