Benchmark KLEE TBF Test-Suite Validator
Tool KLEE 2.0.0-pre-test-comp Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-05 21:09:47 CET 2019-02-06 06:16:47 CET
Run set klee.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-klee.test-comp19_prop-coverage-branches.ReachSafety-BitVectors
Options --verbose --sequence-file cov-seq.txt -r --test-suite ../../results-verified/klee.2019-02-05_2109.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml false(unreach-call) .983 prog tests 26 inspect .75 .77 23 11   .020 0   true prog tests 1 inspect
98.3  100    .21 .26 16 .60  0  
bitvector/byte_add_1-1.yml done .733 prog tests 14 inspect .26 .28 21 2.1 .020 0   unknown prog tests 0 inspect
73.3  82.8  .17 .16 16 .35  0  
bitvector/byte_add_2-2.yml done .75  prog tests 16 inspect .23 .24 21 2.4 .020 0   unknown prog tests 0 inspect
75.0  82.8  .19 .19 16 .39  0  
bitvector/gcd_1.yml done .833 prog tests 10 inspect .14 .14 21 1.7 .016 0   unknown prog tests 0 inspect
83.3  94.7  .17 .17 17 .23  0  
bitvector/gcd_2.yml done .9   prog tests 11 inspect 3.1  3.1  26 38   .016 0   unknown prog tests 0 inspect
90.0  94.7  .15 .15 16 .24  0  
bitvector/gcd_3.yml done .9   prog tests 11 inspect 3.7  3.7  27 45   .016 0   unknown prog tests 0 inspect
90.0  94.7  .15 .15 16 .24  0  
bitvector/interleave_bits.yml done .75  prog tests 1 inspect .13 .15 21 1.3 .016 0   unknown prog tests 0 inspect
75.0  95.8  .12 .12 16 .078 0  
bitvector/modulus-2.yml done .9   prog tests 11 inspect 320    320    84 4200   .016 0   unknown prog tests 0 inspect
90.0  95.2  .15 .15 16 .24  0  
bitvector/num_conversion_2.yml done .833 prog tests 5 inspect .39 .42 21 6.2 .016 0   unknown prog tests 0 inspect
83.3  93.8  .12 .12 17 .14  0  
bitvector/parity.yml done .875 prog tests 5 inspect 1.2  1.2  23 16   .016 0   unknown prog tests 0 inspect
87.5  95.7  .13 .14 16 .12  0  
bitvector/s3_clnt_1.BV.c.cil-1.yml done .790 prog tests 92 inspect 1.7  1.8  31 24   .029 0   unknown prog tests 0 inspect
79.0  88.5  .63 .68 17 6.1   0  
bitvector/s3_clnt_1.BV.c.cil-2.yml timeout (false(unreach-call)) .938 prog tests 116 inspect 900    900    540 10000   .057 0   true prog tests 1 inspect
93.8  95.6  .81 .98 17 7.7   0  
bitvector/s3_clnt_2.BV.c.cil-1.yml done .775 prog tests 91 inspect 1.7  1.7  31 26   .029 0   unknown prog tests 0 inspect
77.5  88.1  .64 .63 17 6.0   0  
bitvector/s3_clnt_2.BV.c.cil-2.yml timeout (false(unreach-call)) .938 prog tests 123 inspect 900    900    450 10000   .061 0   true prog tests 1 inspect
93.8  95.8  .84 .96 17 8.1   0  
bitvector/s3_clnt_3.BV.c.cil-1.yml done .778 prog tests 89 inspect 1.7  1.8  31 26   .029 0   unknown prog tests 0 inspect
77.8  88.2  .63 .62 17 5.9   0  
bitvector/s3_clnt_3.BV.c.cil-2.yml false(unreach-call) .636 prog tests 71 inspect .33 .33 23 4.7 .029 0   true prog tests 1 inspect
63.6  71.8  .60 .58 17 4.7   0  
bitvector/s3_srvr_1.BV.c.cil.yml timeout .787 prog tests 101 inspect 900    900    580 9900   .061 0   unknown prog tests 0 inspect
78.7  81.0  .67 .68 17 7.8   0  
bitvector/s3_srvr_1_alt.BV.c.cil.yml timeout .0   prog tests 106 inspect 900    900    570 10000   .057 0   unknown prog tests 0 inspect
.00 7.03 .70 .70 17 8.3   0  
bitvector/s3_srvr_3.BV.c.cil.yml timeout .828 prog tests 96 inspect 900    900    310 9500   .061 0   unknown prog tests 0 inspect
82.8  84.8  .66 .71 17 7.1   0  
bitvector/s3_srvr_3_alt.BV.c.cil.yml timeout .828 prog tests 95 inspect 900    900    320 9800   .061 0   unknown prog tests 0 inspect
82.8  84.9  .71 .68 17 7.1   0  
bitvector/soft_float_1-2.c.cil.yml done .689 prog tests 31 inspect 370    370    260 5000   .025 0   unknown prog tests 0 inspect
68.9  69.8  .24 .26 17 .91  0  
bitvector/soft_float_1-3.c.cil.yml false(unreach-call) .703 prog tests 32 inspect 370    370    260 5700   .025 0   true prog tests 1 inspect
70.3  70.4  .24 .26 17 .99  0  
bitvector/soft_float_2.c.cil.yml done .688 prog tests 18 inspect 93    93    110 1100   .020 0   unknown prog tests 0 inspect
68.8  70.2  .19 .18 16 .51  0  
bitvector/soft_float_3.c.cil.yml done .708 prog tests 19 inspect 230    230    210 2600   .020 0   unknown prog tests 0 inspect
70.8  71.0  .19 .18 17 .54  0  
bitvector/soft_float_4-2.c.cil.yml done .595 prog tests 23 inspect 360    360    260 4000   .020 0   unknown prog tests 0 inspect
59.5  64.6  .21 .20 17 .63  0  
bitvector/soft_float_4-3.c.cil.yml false(unreach-call) .619 prog tests 24 inspect 360    360    260 4600   .020 0   true prog tests 1 inspect
61.9  65.3  .21 .19 17 .66  0  
bitvector/soft_float_5.c.cil.yml done .688 prog tests 20 inspect 89    89    110 1200   .020 0   unknown prog tests 0 inspect
68.8  70.2  .20 .19 17 .56  0  
bitvector/sum02-1.yml timeout .5   prog tests 3 inspect 900    900    2400 11000   .066 0   unknown prog tests 0 inspect
50.0  88.9  20    20    16 .11  0  
bitvector/sum02-2.yml timeout .5   prog tests 4 inspect 900    900    2400 12000   .070 0   unknown prog tests 0 inspect
50.0  92.3  20    20    16 .13  0  
bitvector-regression/recHanoi03-1.yml timeout (false(unreach-call)) .875 prog tests 8 inspect 900    900    4100 13000   .049 0   true prog tests 1 inspect
87.5  100    .14 .15 20 .19  0  
bitvector-loops/diamond_2-1.yml false(unreach-call) 1.0   prog tests 13 inspect .12 .12 21 1.2 .016 0   true prog tests 1 inspect
100    100    .16 .22 17 .27  0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml false(unreach-call) .875 prog tests 5 inspect .19 .21 22 1.7 .016 0   true prog tests 1 inspect
87.5  100    .15 .15 16 .14  0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 32 24.2  10000 10000 14000 120000 1.0  0   32 2420 2680 51 51 540 77 0  
Run set klee.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-klee.test-comp19_prop-coverage-branches.ReachSafety-BitVectors