Benchmark PRtest TBF Test-Suite Validator
Tool tbf v0.3.0-testcomp19 Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon010; apollon052; apollon080; apollon107; apollon135; apollon167]
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-06 06:02:44 CET 2019-02-06 13:26:19 CET
Run set prtest.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-prtest.test-comp19_prop-coverage-branches.ReachSafety-BitVectors
Options --stats -i random --write-xml --svcomp-nondets --verbose --sequence-file cov-seq.txt -r --test-suite ../../results-verified/prtest.2019-02-06_0602.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml done .7    prog tests 2 inspect .26 .45 31 3.3 0     0   unknown prog tests 0 inspect
70.0  78.1  .13  .13  16   .11  0  
bitvector/byte_add_1-1.yml timeout .733  prog tests 5 inspect 900    840    30 11000   .012 0   unknown prog tests 0 inspect
73.3  82.8  .14  .14  16   .17  0  
bitvector/byte_add_2-2.yml timeout .75   prog tests 5 inspect 900    840    31 14000   .012 0   unknown prog tests 0 inspect
75.0  82.8  .14  .14  16   .17  0  
bitvector/gcd_1.yml timeout .833  prog tests 4 inspect 900    840    31 11000   .012 0   unknown prog tests 0 inspect
83.3  94.7  .13  .13  17   .13  0  
bitvector/gcd_2.yml timeout .9    prog tests 3 inspect 900    840    31 13000   .012 0   unknown prog tests 0 inspect
90.0  94.7  .12  .12  16   .11  0  
bitvector/gcd_3.yml timeout .9    prog tests 3 inspect 900    840    31 11000   .012 0   unknown prog tests 0 inspect
90.0  94.7  .13  .12  17   .11  0  
bitvector/interleave_bits.yml timeout .0    prog tests 1 inspect 900    850    31 14000   .012 0   unknown prog tests 0 inspect
0    0    .11  .11  16   .078 0  
bitvector/modulus-2.yml timeout .0    prog tests 1 inspect 900    850    31 11000   .012 0   unknown prog tests 0 inspect
.00 19.1  .12  .12  17   .078 0  
bitvector/num_conversion_2.yml timeout .0    prog tests 1 inspect 900    850    31 13000   .012 0   unknown prog tests 0 inspect
0    0    .13  .13  16   .078 0  
bitvector/parity.yml timeout .875  prog tests 2 inspect 900    840    31 13000   .012 0   unknown prog tests 0 inspect
87.5  95.7  .13  .13  16   .094 0  
bitvector/s3_clnt_1.BV.c.cil-1.yml timeout .426  prog tests 10 inspect 900    830    31 14000   .012 0   unknown prog tests 0 inspect
42.6  54.4  .25  .25  17   .71  0  
bitvector/s3_clnt_1.BV.c.cil-2.yml timeout .426  prog tests 10 inspect 900    830    31 13000   .012 0   unknown prog tests 0 inspect
42.6  54.6  .27  .26  17   .71  0  
bitvector/s3_clnt_2.BV.c.cil-1.yml timeout .0188 prog tests 1 inspect 900    850    30 15000   .012 0   unknown prog tests 0 inspect
1.88 19.1  .20  .20  17   .12  0  
bitvector/s3_clnt_2.BV.c.cil-2.yml timeout .0188 prog tests 1 inspect 900    850    31 11000   .012 0   unknown prog tests 0 inspect
1.88 19.2  .21  .21  17   .12  0  
bitvector/s3_clnt_3.BV.c.cil-1.yml timeout .0247 prog tests 1 inspect 900    850    31 14000   .012 0   unknown prog tests 0 inspect
2.47 19.5  .20  .20  17   .12  0  
bitvector/s3_clnt_3.BV.c.cil-2.yml timeout .0370 prog tests 2 inspect 900    850    31 12000   .012 0   unknown prog tests 0 inspect
3.70 19.9  .21  .21  17   .18  0  
bitvector/s3_srvr_1.BV.c.cil.yml timeout .383  prog tests 9 inspect 900    830    31 12000   .012 0   unknown prog tests 0 inspect
38.3  45.8  .26  .27  17   .75  0  
bitvector/s3_srvr_1_alt.BV.c.cil.yml timeout .0    prog tests 5 inspect 900    840    31 15000   .012 0   unknown prog tests 0 inspect
.00 7.03 .24  .24  17   .44  0  
bitvector/s3_srvr_3.BV.c.cil.yml timeout .391  prog tests 6 inspect 900    830    31 13000   .012 0   unknown prog tests 0 inspect
39.1  47.5  .25  .27  17   .48  0  
bitvector/s3_srvr_3_alt.BV.c.cil.yml timeout .391  prog tests 6 inspect 900    830    31 13000   .012 0   unknown prog tests 0 inspect
39.1  47.3  .23  .23  17   .49  0  
bitvector/soft_float_1-2.c.cil.yml timeout .689  prog tests 10 inspect 900    830    31 11000   .012 0   unknown prog tests 0 inspect
68.9  69.8  .17  .16  16   .36  0  
bitvector/soft_float_1-3.c.cil.yml done .0    prog tests 0 inspect .25 .44 31 3.1 0     0   unknown prog tests 0 inspect
0    0    .065 .065 9.0 0     0  
bitvector/soft_float_2.c.cil.yml timeout .688  prog tests 8 inspect 900    830    31 14000   .012 0   unknown prog tests 0 inspect
68.8  70.2  .17  .16  16   .27  0  
bitvector/soft_float_3.c.cil.yml timeout .604  prog tests 8 inspect 900    830    31 13000   .012 0   unknown prog tests 0 inspect
60.4  64.1  .16  .15  17   .27  0  
bitvector/soft_float_4-2.c.cil.yml timeout .595  prog tests 8 inspect 900    830    31 12000   .012 0   unknown prog tests 0 inspect
59.5  64.6  .15  .15  16   .26  0  
bitvector/soft_float_4-3.c.cil.yml done .0    prog tests 0 inspect .28 .46 30 2.7 0     0   unknown prog tests 0 inspect
0    0    .070 .070 9.0 0     0  
bitvector/soft_float_5.c.cil.yml timeout .688  prog tests 7 inspect 900    830    31 14000   .012 0   unknown prog tests 0 inspect
68.8  70.2  .15  .14  17   .24  0  
bitvector/sum02-1.yml done .0    prog tests 0 inspect 7.9  7.7  31 96   0     0   unknown prog tests 0 inspect
0    0    .060 .061 9.0 0     0  
bitvector/sum02-2.yml timeout .5    prog tests 1 inspect 900    850    31 12000   .012 0   unknown prog tests 0 inspect
50.0  92.3  6.3   6.3   16   .078 0  
bitvector-regression/recHanoi03-1.yml done .125  prog tests 1 inspect .25 .44 30 2.9 0     0   unknown prog tests 0 inspect
12.5  33.3  .11  .11  16   .078 0  
bitvector-loops/diamond_2-1.yml done .0    prog tests 0 inspect .24 .43 31 3.4 0     0   unknown prog tests 0 inspect
0    0    .060 .061 9.0 0     0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml timeout .875  prog tests 3 inspect 900    840    31 12000   .012 0   unknown prog tests 0 inspect
87.5  94.7  .12  .12  16   .11  0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 32 12.6 23000 22000 980 330000 .32 0   32 1260 1540 11 11 500 6.9 0  
Run set prtest.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-prtest.test-comp19_prop-coverage-branches.ReachSafety-BitVectors