Benchmark PRtest TBF Test-Suite Validator
Tool tbf v0.3.0-testcomp19 Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon010; apollon052; apollon080; apollon107; apollon135; apollon167]
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-06 06:02:44 CET 2019-02-06 13:26:19 CET
Run set prtest.test-comp19_prop-coverage-error-call.ReachSafety-BitVectors tbf-testsuite-validator-prtest.test-comp19_prop-coverage-error-call.ReachSafety-BitVectors
Options --stats -i random --write-xml --svcomp-nondets --verbose --sequence-file cov-seq.txt -r --stop-after-found-violation --test-suite ../../results-verified/prtest.2019-02-06_0602.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml unknown 1 prog tests 3 inspect .26 .45 31 3.0 0     0   true prog tests 1 inspect
66.7  76.6 .13 .13 16 .11  0  
bitvector/s3_clnt_1.BV.c.cil-2.yml timeout prog tests 10 inspect 900    830    31 15000   .012 0   unknown prog tests 0 inspect
42.6  54.6 .24 .24 17 .71  0  
bitvector/s3_clnt_2.BV.c.cil-2.yml timeout prog tests 1 inspect 900    850    31 13000   .012 0   unknown prog tests 0 inspect
1.88 19.2 .21 .21 17 .12  0  
bitvector/s3_clnt_3.BV.c.cil-2.yml timeout prog tests 2 inspect 900    850    31 10000   .012 0   unknown prog tests 0 inspect
3.70 19.9 .21 .23 17 .18  0  
bitvector/soft_float_1-3.c.cil.yml unknown 1 prog tests 1 inspect .26 .45 31 2.9 0     0   true prog tests 1 inspect
18.9  31.4 .14 .14 17 .098 0  
bitvector/soft_float_4-3.c.cil.yml unknown 1 prog tests 1 inspect .26 .44 31 3.4 0     0   true prog tests 1 inspect
23.8  35.4 .13 .13 16 .090 0  
bitvector/sum02-1.yml unknown 1 prog tests 1 inspect 7.9  7.7  31 100   0     0   true prog tests 1 inspect
62.5  88.9 7.3  7.3  16 .078 0  
bitvector-regression/recHanoi03-1.yml error (0) prog tests 1 inspect .25 .43 31 3.5 0     0   unknown prog tests 0 inspect
12.5  33.3 .12 .12 16 .078 0  
bitvector-loops/diamond_2-1.yml unknown 1 prog tests 1 inspect .29 .48 31 2.9 0     0   true prog tests 1 inspect
54.2  96.5 .12 .12 17 .078 0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml timeout prog tests 3 inspect 900    840    31 12000   .012 0   unknown prog tests 0 inspect
87.5  94.7 .15 .14 16 .11  0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 10 5 3600 3400 310 51000 .049 0   10 374 550 8.7 8.7 170 1.7 0  
Run set prtest.test-comp19_prop-coverage-error-call.ReachSafety-BitVectors tbf-testsuite-validator-prtest.test-comp19_prop-coverage-error-call.ReachSafety-BitVectors