Benchmark VeriFuzz TBF Test-Suite Validator
Tool VeriFuzz 1.0.1 Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-06 07:17:17 CET 2019-02-06 14:51:38 CET
Run set verifuzz.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-verifuzz.test-comp19_prop-coverage-branches.ReachSafety-BitVectors
Options --testcomp --verbose --sequence-file cov-seq.txt -r --test-suite ../../results-verified/verifuzz.2019-02-06_0717.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml error .983 prog tests 25 inspect 880 900 160 13000 2000    0   true prog tests 1 inspect
98.3  100    .20 .19 16 .58  0  
bitvector/byte_add_1-1.yml error .733 prog tests 7 inspect 890 900 160 13000 .85 0   unknown prog tests 0 inspect
73.3  82.8  .14 .14 16 .21  0  
bitvector/byte_add_2-2.yml error .75  prog tests 7 inspect 890 900 160 13000 .91 0   unknown prog tests 0 inspect
75.0  82.8  .14 .14 16 .21  0  
bitvector/gcd_1.yml timeout .75  prog tests 3 inspect 900 920 150 12000 1.0  0   unknown prog tests 0 inspect
75.0  94.7  .12 .12 16 .11  0  
bitvector/gcd_2.yml timeout .9   prog tests 18 inspect 900 920 150 13000 1.2  0   unknown prog tests 0 inspect
90.0  94.7  .18 .17 16 .36  0  
bitvector/gcd_3.yml timeout .9   prog tests 17 inspect 900 920 150 11000 1.1  0   unknown prog tests 0 inspect
90.0  94.7  .17 .18 16 .34  0  
bitvector/interleave_bits.yml timeout .75  prog tests 2 inspect 900 920 150 11000 1.2  0   unknown prog tests 0 inspect
75.0  95.8  .12 .12 16 .094 0  
bitvector/modulus-2.yml timeout .9   prog tests 18 inspect 900 920 150 9800 1.2  0   unknown prog tests 0 inspect
90.0  95.2  .17 .16 16 .36  0  
bitvector/num_conversion_2.yml timeout .833 prog tests 15 inspect 900 920 150 11000 1.2  0   unknown prog tests 0 inspect
83.3  93.8  .16 .15 16 .31  0  
bitvector/parity.yml timeout .875 prog tests 16 inspect 900 920 150 12000 1.1  0   unknown prog tests 0 inspect
87.5  95.7  .17 .17 16 .32  0  
bitvector/s3_clnt_1.BV.c.cil-1.yml timeout .790 prog tests 76 inspect 900 920 200 11000 1.9  0   unknown prog tests 0 inspect
79.0  88.5  .56 .55 17 5.0   0  
bitvector/s3_clnt_1.BV.c.cil-2.yml error .907 prog tests 197 inspect 890 900 200 11000 63    0   true prog tests 1 inspect
90.7  94.1  1.3  1.3  17 13     0  
bitvector/s3_clnt_2.BV.c.cil-1.yml timeout .775 prog tests 68 inspect 900 920 200 12000 1.7  0   unknown prog tests 0 inspect
77.5  88.1  .50 .50 17 4.5   0  
bitvector/s3_clnt_2.BV.c.cil-2.yml error .938 prog tests 195 inspect 890 900 200 11000 230    0   true prog tests 1 inspect
93.8  95.8  1.2  1.2  17 13     0  
bitvector/s3_clnt_3.BV.c.cil-1.yml timeout .778 prog tests 78 inspect 900 920 200 9700 1.9  0   unknown prog tests 0 inspect
77.8  88.2  .58 .54 17 5.2   0  
bitvector/s3_clnt_3.BV.c.cil-2.yml error .636 prog tests 62 inspect 890 900 200 12000 690    0   true prog tests 1 inspect
63.6  71.8  .52 .49 17 4.1   0  
bitvector/s3_srvr_1.BV.c.cil.yml timeout .787 prog tests 134 inspect 900 920 210 11000 2.4  0   unknown prog tests 0 inspect
78.7  81.0  .82 .75 17 10     0  
bitvector/s3_srvr_1_alt.BV.c.cil.yml timeout .0   prog tests 8 inspect 900 920 210 11000 1.2  0   unknown prog tests 0 inspect
.00 7.03 .25 .25 17 .67  0  
bitvector/s3_srvr_3.BV.c.cil.yml timeout .822 prog tests 129 inspect 900 920 210 9800 2.3  0   unknown prog tests 0 inspect
82.2  84.5  .81 .75 17 9.6   0  
bitvector/s3_srvr_3_alt.BV.c.cil.yml timeout .828 prog tests 150 inspect 900 920 210 8800 2.8  0   unknown prog tests 0 inspect
82.8  84.9  .90 .82 17 11     0  
bitvector/soft_float_1-2.c.cil.yml timeout .689 prog tests 31 inspect 900 920 170 11000 1.4  0   unknown prog tests 0 inspect
68.9  69.8  .24 .22 17 .96  0  
bitvector/soft_float_1-3.c.cil.yml error .703 prog tests 30 inspect 890 900 160 13000 4300    0   true prog tests 1 inspect
70.3  70.4  .24 .22 17 .93  0  
bitvector/soft_float_2.c.cil.yml timeout .688 prog tests 24 inspect 900 920 160 12000 1.3  0   unknown prog tests 0 inspect
68.8  70.2  .22 .25 16 .66  0  
bitvector/soft_float_3.c.cil.yml timeout .708 prog tests 25 inspect 900 920 160 12000 1.3  0   unknown prog tests 0 inspect
70.8  71.0  .23 .21 17 .68  0  
bitvector/soft_float_4-2.c.cil.yml timeout .595 prog tests 29 inspect 900 920 170 11000 1.3  0   unknown prog tests 0 inspect
59.5  64.6  .21 .21 16 .78  0  
bitvector/soft_float_4-3.c.cil.yml error .619 prog tests 30 inspect 890 900 160 12000 3300    0   true prog tests 1 inspect
61.9  65.3  .25 .24 17 .80  0  
bitvector/soft_float_5.c.cil.yml timeout .688 prog tests 25 inspect 900 920 160 9700 1.2  0   unknown prog tests 0 inspect
68.8  70.2  .23 .21 17 .68  0  
bitvector/sum02-1.yml timeout .875 prog tests 13 inspect 900 900 150 11000 1.1  0   true prog tests 1 inspect
87.5  100    .15 .14 16 .27  0  
bitvector/sum02-2.yml timeout .5   prog tests 12 inspect 900 900 150 12000 .69 0   unknown prog tests 0 inspect
50.0  92.3  .15 .14 16 .26  0  
bitvector-regression/recHanoi03-1.yml timeout .875 prog tests 12 inspect 900 900 150 13000 12    0   true prog tests 1 inspect
87.5  100    .16 .16 16 .26  0  
bitvector-loops/diamond_2-1.yml error 1.0   prog tests 8 inspect 880 900 150 13000 4100    0   true prog tests 1 inspect
100    100    .17 .17 16 .19  0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml error 1.0   prog tests 15 inspect 880 900 150 11000 77    0   true prog tests 1 inspect
100    100    .19 .19 16 .31  0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 32 24.6 29000 29000 5500 370000 15000 0   32 2460 2690 12 11 530 86 0  
Run set verifuzz.test-comp19_prop-coverage-branches.ReachSafety-BitVectors tbf-testsuite-validator-verifuzz.test-comp19_prop-coverage-branches.ReachSafety-BitVectors