Benchmark VeriFuzz TBF Test-Suite Validator
Tool VeriFuzz 1.0.1 Tbf Test-suite Validator v1.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 10800 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-45-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2019-02-06 07:17:17 CET 2019-02-06 14:51:38 CET
Run set verifuzz.test-comp19_prop-coverage-error-call.ReachSafety-BitVectors tbf-testsuite-validator-verifuzz.test-comp19_prop-coverage-error-call.ReachSafety-BitVectors
Options --testcomp --verbose --sequence-file cov-seq.txt -r --stop-after-found-violation --test-suite ../../results-verified/verifuzz.2019-02-06_0717.logfiles/${rundefinition_name}.${inputfile_name}.files/test-suite.zip
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add-1.yml done 1 prog tests 1 inspect 4.1 2.3 160 40 1.8  0   true prog tests 1 inspect
58.3 81.2 .13 .14 17 .086 0  
bitvector/s3_clnt_1.BV.c.cil-2.yml done 1 prog tests 1 inspect 130   130   200 1600 .82 0   true prog tests 1 inspect
28.4 43.7 .27 .27 17 .12  0  
bitvector/s3_clnt_2.BV.c.cil-2.yml done 1 prog tests 1 inspect 670   680   200 7800 1.6  0   true prog tests 1 inspect
28.8 41.0 .27 .27 17 .12  0  
bitvector/s3_clnt_3.BV.c.cil-2.yml done 1 prog tests 1 inspect 40   38   200 430 .68 0   true prog tests 1 inspect
22.2 37.7 .26 .26 17 .12  0  
bitvector/soft_float_1-3.c.cil.yml done 1 prog tests 1 inspect 4.8 2.6 170 49 1.0  0   true prog tests 1 inspect
21.6 33.7 .15 .15 16 .098 0  
bitvector/soft_float_4-3.c.cil.yml done 1 prog tests 1 inspect 4.3 2.5 170 42 1.0  0   true prog tests 1 inspect
33.3 40.9 .16 .16 16 .090 0  
bitvector/sum02-1.yml done 1 prog tests 1 inspect 9.6 8.2 150 100 .55 0   true prog tests 1 inspect
62.5 88.9 .11 .11 16 .078 0  
bitvector-regression/recHanoi03-1.yml done 1 prog tests 1 inspect 8.7 7.4 150 88 .66 0   true prog tests 1 inspect
50.0 83.3 .12 .12 16 .078 0  
bitvector-loops/diamond_2-1.yml done 1 prog tests 1 inspect 3.3 1.9 150 37 .48 0   true prog tests 1 inspect
54.2 96.5 .11 .11 17 .078 0  
bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.yml done 1 prog tests 1 inspect 6.2 4.9 150 85 .57 0   true prog tests 1 inspect
75.0 89.5 .12 .12 16 .078 0  
sv-benchmarks/c/ status score program test-suite TS size inspect test-suite cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status program test-suite TS size inspect test-suite cov branch cov (%) line cov (%) cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 10 10 880 880 1700 10000 9.1 0   10 434 637 1.7 1.7 170 .94 0  
Run set verifuzz.test-comp19_prop-coverage-error-call.ReachSafety-BitVectors tbf-testsuite-validator-verifuzz.test-comp19_prop-coverage-error-call.ReachSafety-BitVectors