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ULTIMATE TestGen 2024-12-20 16:19:19 CET utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash

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TestCov 2024-12-24 10:05:48 CET testcov-validate-test-suites-clang-formatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash

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TestCov 2024-12-24 10:05:48 CET testcov-validate-test-suites-clang-unformatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash

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TestCov 2024-12-24 10:05:47 CET testcov-validate-test-suites-gcc-formatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash

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TestCov 2024-12-24 10:05:47 CET testcov-validate-test-suites-gcc-unformatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash

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Summary Table Quantile Plot Scatter Plot Info

Benchmark Setup

BenchmarkUTestGenTestCov
ToolULTIMATE TestGen 0.2.3-222e02f9TestCov 3.11
Limitstimelimit: 900 s, memlimit: 15000 MB, CPU core limit: 4timelimit: 600 s, memlimit: 7000 MB, CPU core limit: 2
Hostapollon*
OSLinux 6.8.0-51-generic
SystemCPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3800 MHz, Turbo Boost: disabled; RAM: 33471 MB
Date of execution2024-12-20 16:19:19 CET2024-12-24 10:05:48 CET2024-12-24 10:05:47 CET
Run setutestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthashtestcov-validate-test-suites-clang-formatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthashtestcov-validate-test-suites-clang-unformatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthashtestcov-validate-test-suites-gcc-formatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthashtestcov-validate-test-suites-gcc-unformatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash
Options
  • --traceabstraction.test.generation.mode Standard
  • --rcfgbuilder.reuse.mode.for.test.generation ReuseUNSATmatchPrefix
  • --full-output
  • --memlimit 6GB
  • --timelimit-per-run 50
  • --format
  • --verbose
  • --no-plots
  • --prep-cgroup
  • --disable-info-files
  • --compiler clang
  • --cov-tool llvm-cov
  • --reduction BY_ORDER
  • --reduction-output test-suite
  • --test-suite ../../results-verified/utestgen.2024-12-20_16-19-19.files/${rundefinition_name}/${taskdef_name}/test-suite.zip
  • --memlimit 6GB
  • --timelimit-per-run 50
  • --verbose
  • --no-plots
  • --prep-cgroup
  • --disable-info-files
  • --compiler clang
  • --cov-tool llvm-cov
  • --reduction BY_ORDER
  • --reduction-output test-suite
  • --test-suite ../../results-verified/utestgen.2024-12-20_16-19-19.files/${rundefinition_name}/${taskdef_name}/test-suite.zip
  • --memlimit 6GB
  • --timelimit-per-run 50
  • --format
  • --verbose
  • --no-plots
  • --prep-cgroup
  • --disable-info-files
  • --reduction BY_ORDER
  • --reduction-output test-suite
  • --test-suite ../../results-verified/utestgen.2024-12-20_16-19-19.files/${rundefinition_name}/${taskdef_name}/test-suite.zip
  • --memlimit 6GB
  • --timelimit-per-run 50
  • --verbose
  • --no-plots
  • --prep-cgroup
  • --disable-info-files
  • --reduction BY_ORDER
  • --reduction-output test-suite
  • --test-suite ../../results-verified/utestgen.2024-12-20_16-19-19.files/${rundefinition_name}/${taskdef_name}/test-suite.zip
Propertiescoverage-branches

Statistics

ULTIMATE TestGen 2024-12-20 16:19:19 CET utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash
TestCov 2024-12-24 10:05:48 CET testcov-validate-test-suites-clang-formatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash
TestCov 2024-12-24 10:05:48 CET testcov-validate-test-suites-clang-unformatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash
TestCov 2024-12-24 10:05:47 CET testcov-validate-test-suites-gcc-formatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash
TestCov 2024-12-24 10:05:47 CET testcov-validate-test-suites-gcc-unformatted-utestgen.Test-Comp25_coverage-branches.SoftwareSystems-uthash
Click here to select columns
 
status
score
cpu
(s)
wall
(s)
mem
(MB)
 
status
cov
(%)
cpu
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wall
(s)
mem
(MB)
 
status
cov
(%)
cpu
(s)
wall
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status
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cpu
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status
cov
(%)
cpu
(s)
wall
(s)
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(MB)
all results
51
25.6
46000
43000
68000
51
2520
350
400
4300
51
2520
340
390
4300
51
2560
310
370
4000
51
2560
310
360
4000

Generated by BenchExec 3.29