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ULTIMATE TestGen 2024-12-20 16:19:19 CET utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
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TestCov 2024-12-24 10:05:48 CET testcov-validate-test-suites-clang-formatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
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TestCov 2024-12-24 10:05:48 CET testcov-validate-test-suites-clang-unformatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
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TestCov 2024-12-24 10:05:47 CET testcov-validate-test-suites-gcc-formatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
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TestCov 2024-12-24 10:05:47 CET testcov-validate-test-suites-gcc-unformatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
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Benchmark Setup
Benchmark | UTestGen | TestCov | |||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Tool | ULTIMATE TestGen 0.2.3-222e02f9 | TestCov 3.11 | |||||||||||||||||||||||||||||||||||||||||||||||
Limits | timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 4 | timelimit: 600 s, memlimit: 7000 MB, CPU core limit: 2 | |||||||||||||||||||||||||||||||||||||||||||||||
Host | apollon* | ||||||||||||||||||||||||||||||||||||||||||||||||
OS | Linux 6.8.0-51-generic | ||||||||||||||||||||||||||||||||||||||||||||||||
System | CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3800 MHz, Turbo Boost: disabled; RAM: 33471 MB | ||||||||||||||||||||||||||||||||||||||||||||||||
Date of execution | 2024-12-20 16:19:19 CET | 2024-12-24 10:05:48 CET | 2024-12-24 10:05:47 CET | ||||||||||||||||||||||||||||||||||||||||||||||
Run set | utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow | testcov-validate-test-suites-clang-formatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow | testcov-validate-test-suites-clang-unformatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow | testcov-validate-test-suites-gcc-formatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow | testcov-validate-test-suites-gcc-unformatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow | ||||||||||||||||||||||||||||||||||||||||||||
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Properties | coverage-error-call |
Statistics
ULTIMATE TestGen 2024-12-20 16:19:19 CET utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
TestCov 2024-12-24 10:05:48 CET testcov-validate-test-suites-clang-formatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
TestCov 2024-12-24 10:05:48 CET testcov-validate-test-suites-clang-unformatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
TestCov 2024-12-24 10:05:47 CET testcov-validate-test-suites-gcc-formatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
TestCov 2024-12-24 10:05:47 CET testcov-validate-test-suites-gcc-unformatted-utestgen.Test-Comp25_coverage-error-call.ReachSafety-ControlFlow
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all results
5
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5
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5
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410
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